During the International Supercomputing Conference (ISC), Intel Corporation discussed its strategy to lead the industry in the era of Exascale computing, and the critical role that the Intel® Many Integrated Core (MIC) architecture will play. Intel's relentless pursuit of Moore's Law combined with an innovative highly efficient programming model and extreme system scalability are the key ingredients for crossing the threshold from Petascale computing to Exascale computing. During ISC, Intel also discussed the progress of Intel MIC architecture, with software development platforms currently shipping to select partners. Intel and some of its partners such as Forschungszentrum Jueilch, Leibniz Supercomputing Centre (LRZ), CERN and Korea Institute of Science and Technology Information (KISTI) showed early results of their work with the "Knights Ferry" software development platform, demonstrating both performance and programmability. Server and workstation platforms from SGI, Dell, HP, IBM, Colfax and Supermicro, who are planning products supporting "Knights Corner," were also showcased at ISC.
back to topPress Materials
- Fact Sheet: Intel® Many Integrated Core (Intel® MIC) Architecture ISC'11 Demos and Performance Description (PDF 205KB)
- Presentation: Intel®: Accelerating the Path to Exascale (PDF 2.1MB)
- Tech Brief: Parallel Programming. Multicore processors TODAY, many-core co-processors READY. (PDF 574KB)
- Tech Brief: Intel® Many Integrated Core (MIC) Architecture – Performance and Programmability (PDF 1MB)
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Die shot of Intel® MIC Architecture co-processor codenamed "Auburn Isle" - heart of "Knights Ferry" SDP card.